1. Field of the Invention
The present invention relates to a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) and, more particularly, to the technical field of a semiconductor memory device which is designed to generate and store check codes in a row direction and a column direction of a storage area to perform error detection/correction by using the check codes and an error correction method thereof.
2. Related Art
In order to realize a further reduction in power consumption in a data holding state of a DRAM, a refresh operation is required to be controlled in a period longer than a period in a normal operation. For this reason, a configuration which is equipped with an error correction function achieved by an ECC circuit or the like to make it possible to correct bit errors which is increased in number by elongating the period of the refresh operation is proposed. For example, a semiconductor integrated circuit device disclosed in Japanese Patent Laid-Open Application No. 2002-56671 is a typical configuration.
The semiconductor integrated circuit device disclosed in Japanese Patent Laid-Open Application No. 2002-56671 includes a means to hold check bits for error detection/correction, a means to generate check bits from a number of data, and a means to correct error bits by using check bits. The semiconductor integrated circuit has a configuration which generates and stores check bits in a change to a data holding state. This configuration makes it possible to elongate the period of a refresh operation, and low power consumption in the data holding state can be achieved.
However, with the conventional configuration, when bit errors increase in number beyond the bounds of permissibility, an error pattern the error of which cannot be corrected often occurs. For example, according to a general error correction circuit applied to a DRAM, only an error of 1 bit which is generated in a bit string in a row or column direction can be corrected. However, an error of two or more bits which is generated in the row or column direction cannot be corrected. On the other hand, the configuration of an error correction circuit which can correct an error of two or more generated in a bit string may also be employed as an error correction circuit. However, such an error correction circuit increases in circuit scale to increase the cost. Therefore, in the conventional configuration, a refresh period must be limited to a specific period to suppress an error occurrence rate within an error-correctable range. The low power consumption cannot be achieved without any problem.